DES has not been considered safe for a long time. For some time now, cracking tool John the Ripp has even made it possible to accelerate cracking with FPGAs. Since I find this topic exciting, I tried it with an …
Investigation into DES cracking with John the Ripper and Ztex FPGA Read more »
Demo of how communication load can influence the cycle time of a PLC. Default main cyclic task is used. Cycle time is set to 1ms. Every 250 cycles the next output is set. Attack on different PLCs Attack Code #!/bin/bash …
The OpenPLC is a opensource Programmable Logic Controllers (PLC) alternative. Due to this, it is possible to understand the black box of these systems. It could be easily used with a Raspberry Pi.
Coreboot provides a lot of possibilities of configurations, primary and secondary payloads and debugging mechanisms.
Coreboot is an Open Source project, which replaces the proprietary BIOS of a traditional computer. Coreboot initialize the Hardware and then executes a payload (e. g. SeaBIOS or Grub).
With OpenOCD it is possible to flash/upload programs to the spi flash of the Arty Board. From there the SiFive Risc-V “core” will boot.
Configuring and programming the 100 € Xilinx Arty development board with an open source implementation of the Risc-V ISA from SiFive.
After getting access to the serial interface of the IP-Camera the next step is to get a root shell.
The last article shows, how to identify the serial port on the IP-Camera. With this it is possible to solder wires on the IP-Camera and attach a USB to serial adapter to it.
I have bought an WiFi security camera from banggood. The Digoo BB-M2 Mini WiFi HD 720P costs about 20 €, which is quite cheap for this kind of product. This article will analyze the serial interface of the IP camera.
In my part time I have done my first Offensive Security course and certificate. It is called Wireless Attacks (WiFu) and deals with all kind of wireless attacks.
